Passivation layer for an integrated circuit device that provides a moisture and proton barrier

ABSTRACT

An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from United States ProvisionalApplication for Patent No. 63/126,096, filed Dec. 16, 2020, thedisclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present invention generally relates to integrated circuit devicesand, in particular, to a passivation layer for such an integratedcircuit device that provides a barrier against a contaminant, such asmoisture and proton, intrusion.

BACKGROUND

Reference is made to FIG. 1 which shows a cross-section of a portion ofan integrated circuit device 10. The illustrated device in thisembodiment is a discrete power transistor of, for example, a verticalgate n-channel MOSFET type.

A semiconductor substrate 12 is lightly doped with a first-type dopant(for example, N-type). The semiconductor substrate 12 includes a topsurface 14 and a bottom surface 16. A peripheral edge surface 18 of thesemiconductor substrate 12 joins the top surface 14 and bottom surface16. The semiconductor substrate 12 forms the drain region of thediscrete power transistor. A metal layer 58 at the bottom surface 16provides the drain (D) electrical contact. The metal layer 58 may, forexample, be made of a stack of layers including: a Titanium (Ti) layer;a Nickel (Ni) or alloy of Nickel and Vanadium (NiV) layer; and a Silver(Ag) or Gold (Au) layer.

A plurality of trenches 20 extend into the semiconductor substrate 12from the top surface 14. The trenches 20 have a depth which is less thana thickness of the semiconductor substrate 12. In an embodiment, eachtrench 20 has a width (extending in the plane of the cross-section) anda length (extending perpendicular to the width and in a plane into andout of the cross-section). In an embodiment, the length is substantiallygreater than the width, and thus each trench 20 is a strip trenchextending into and out of the cross-section and having a rectangularshape in top view. Each trench 20 is lined by an insulating liner 22,with the remainder of each trench filled by an electrical conductor 24forming the gate electrode of the discrete power transistor. In anembodiment, the insulating liner 22 is made of a dielectric material,for example an oxide, and the electrical conductor 24 is made of aconducting material, for example polysilicon (that may, if desired, bedoped with a suitable dopant species/type).

The semiconductor substrate 12 further includes a first semiconductorwell 26 that is doped with a second-type dopant (for example, P-type).The first semiconductor well 26 has a depth extending from the topsurface 14 which is less than the depth of the trenches 20. The firstsemiconductor well 26 forms the body (channel) region of the discretepower transistor.

The peripheral termination region PR at the perimeter of thesemiconductor substrate 12 includes a second semiconductor well 27 thatis doped with the second-type dopant (for example, P-type). The secondsemiconductor well 27 has a depth extending from the top surface 14which is greater than the depth of the trenches 20. The secondsemiconductor well 27 forms the ring region of the discrete powertransistor.

The semiconductor substrate 12 further includes a semiconductor region28 that is doped with the first-type dopant. The semiconductor region 28has a depth extending from the top surface 14 which is less than thedepth of the semiconductor well 26. The semiconductor region 28 formsthe source region of the discrete power transistor. The semiconductorregion 28 does not extend across the entire top surface 14 of thesemiconductor substrate 12, but rather is present only in an activeregion AR corresponding generally to the area where the trenches 20 arepresent.

A field oxide region 30 is provided at the top surface 14 of thesemiconductor substrate 12 in the peripheral region PR outside of theactive region AR and adjacent the peripheral edge surface 18. This fieldoxide region 30 may, for example, surround the active region AR.

A premetallization dielectric layer 32 is deposited to cover the topsurface 14 of the semiconductor substrate 12 and the oxide region 30.The premetallization dielectric layer 32 may be made of a dielectricmaterial such as, for example, tetraethyl orthosilicate(tetraethoxysilane—TEOS). In an embodiment, the premetallizationdielectric layer 32 may comprise a stack of layers including a TEOSlayer covering the top surface 14 of the semiconductor substrate 12 andthe oxide region 30 and a Boron and Phosphorus doped TEOS (BPTEOS) layercovering the TEOS layer. In another embodiment, the premetallizationdielectric layer 32 may comprise a stack of layers including a TEOSlayer covering the top surface 14 of the semiconductor substrate 12 andthe oxide region 30 and a Phosphorus doped TEOS (PTEOS) layer coveringthe TEOS layer.

A plurality of trenches 34 extend through the premetallizationdielectric layer 32 and into the semiconductor substrate 12. Thetrenches 34 have a depth which is less than the depth of thesemiconductor well 26 and greater than the depth of the semiconductorregion 28. Thus, the trenches 34 extend fully through thepremetallization dielectric layer 32 and the semiconductor region 28 andpartially into the semiconductor well 26. In an embodiment, each trench34 has a width (extending in the plane of the cross-section) and alength (extending perpendicular to the width and extending in a planeinto and out of the cross-section). In an embodiment, the length issubstantially greater than the width, and thus each trench 34 is a striptrench extending into and out of the cross-section and having arectangular shape in top view. Each trench 34 is located between (andextends parallel to) two trenches 20. The upper surface of thepremetallization dielectric layer 32 and the sidewalls and bottom ofeach trench 34 are lined with a stack of layers 36 comprising, forexample, a thin metal layer and a thin metal nitride layer. The thinmetal layer may, for example, be made of Titanium, and the thin metalnitride layer may, for example, be made of a Titanium Nitride (TiN)material. The remainder of each trench 34 filled by an electricalconductor 38 forming the source and body contact of the discrete powertransistor. The electrical conductor 38 may, for example, be made of aTungsten (W) material.

A first metal layer 42 is deposited over the thin metal nitride layer36. This first metal layer 42 may, for example, be made of Titanium(Ti).

A second metal layer 44 is deposited over the first metal layer 42. Thesecond metal layer 44 may, for example, be made of Aluminum (Al) or analloy of Copper and Aluminum (AlCu).

The second metal layer 44, first metal layer 42 and the metal/metalnitride layer stack 36 are lithographically patterned to define a source(S) electrical contact 46 and a gate (G) electrical contact 48.

The lithographic patterning exposes an upper surface of thepremetallization dielectric layer 32 in areas where the source (S)electrical contact 46 and gate (G) electrical contact 48 are notpresent. A passivation layer 50 is deposited over the source (S)electrical contact 46, the gate (G) electrical contact 48 and theexposed upper surface of the premetallization dielectric layer 32.Detail of the passivation layer 50 configuration at the source (S)electrical contact 46 and gate (G) electrical contact 48 is shown inFIG. 2. In an embodiment, the passivation layer 50 may comprise a TEOSlayer 50 a, or a Silicon Nitride (SiN) layer 50 b, or a stack of layersincluding the TEOS layer 50 a and the Silicon Nitride (SiN) layer 50 b.The TEOS layer 50 a may, for example, have a thickness of about 10,000 Åand the SiN layer 50 b may, for example, have a thickness of about10,000 Å. The passivation layer 50 is lithographically patterned to formopenings exposing an upper surface of the source (S) electrical contact46 and gate (G) electrical contact 48.

The passivation layer 50 is provided to inhibit a contaminant (such asmoisture and proton) intrusion. However, stress can cause cracks to formin the passivation layer 50. Contaminants can enter through the cracksand contribute to device failure. For example, moisture penetration canlead to temperature humidity bias (THB) reliability failure and protonintrusion can cause high temperature reverse bias (HTRB) reliabilityfailure.

There is a need in the art for a passivation layer that can provide foran improved barrier against a contaminant, such as moisture and proton,intrusion.

SUMMARY

In an embodiment, an integrated circuit device comprises: a metalcontact having a top surface and a sidewall, the top surface of themetal contact including a first surface portion, a second surfaceportion and a third surface portion; and a passivation layer extendingon the sidewall of the metal contact and on the first and second surfaceportions of the top surface of the metal contact.

The passivation layer comprises a stack of layers including: atetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS)layer on top of the TEOS layer; and a high-density Silicon-rich Nitridelayer on top of the PTEOS layer.

The TEOS and PTEOS layers extend over the first surface portion of thetop surface of the metal contact, but not over the second and thirdsurface portions of the top surface of the metal contact.

The high-density Silicon-rich Nitride layer extends over the first andsecond surface portions of the top surface of the metal contact, but notover the third surface portion of the top surface of the metal contact.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the embodiments, reference will now bemade by way of example only to the accompanying figures in which:

FIG. 1 shows a cross-section of a portion of an integrated circuitdevice;

FIG. 2 shows detail of a passivation layer configuration at a sourceelectrical contact and a gate electrical contact of the integratedcircuit device of FIG. 1;

FIG. 3 shows detail of a passivation layer configuration at the sourceelectrical contact and the gate electrical contact of the integratedcircuit device of FIG. 1;

FIG. 4 shows a scanning electron micrograph of an example of thepassivation layer configuration;

FIGS. 5A-5E show steps of a fabrication process for making thepassivation layer configuration of FIGS. 3 and 4;

FIG. 6 shows detail of a passivation layer configuration at the sourceelectrical contact and the gate electrical contact of the integratedcircuit device of FIG. 1;

FIG. 7 illustrates a relationship between N/Si ratio and refractiveindex for Si-rich silicon nitride material; and

FIGS. 8A-8C show cross-sections of other integrated circuit devicesutilizing the passivation layer configuration.

DETAILED DESCRIPTION

Reference is now made to FIGS. 3 and 6 which show detail of apassivation layer 50′ configuration at the source electrical contact 46and the gate electrical contact 48 of the integrated circuit device ofFIG. 1. In this embodiment, the passivation layer 50′ comprises a stackof layers including: a TEOS layer 50 a′, a Phosphorus doped TEOS (PTEOS)layer 50 b′ covering the TEOS layer 50 a′, and a Silicon Nitride (SiN)layer 50 c′. The TEOS layer 50 a′ may, for example, have a thickness ina range of about 12,000-16,000 Å, the PTEOS layer 50 b′ may, forexample, have a thickness in a range of about 4,000-6,000 Å, and the SiNlayer 50 c′ may, for example, have a thickness in a range of about8,000-12,000 Å. In the implementation as shown in FIG. 6, adhesion ofthe SiN layer 50 c′ on the metal layer 44 may be enhanced by the use ofa thin Silicon flash layer 70 between the PTEOS layer 50 b′ and the SiNlayer 50 c′. The Silicon flash layer 70 may, for example, have athickness of less than 100 Å. The passivation layer 50′ islithographically patterned to form openings exposing an upper surface ofthe source (S) electrical contact 46 and gate (G) electrical contact 48.

The TEOS layer 50 a′ provides a layer made of a material that is softerthan Silicon Nitride to provide a stress relieving structure and alsopresents a good adhesion property with respect to the Aluminum materialof the second metal layer 44. The TEOS layer 50 a′ also provides adiffusion barrier that inhibits the diffusion of Phosphorus from thePTEOS layer 50 b′. The PTEOS layer 50 b′ functions as a gettering layerpresenting a proton H+ gettering center. The SiN layer 50 c′ ispreferably implemented as a high-density Silicon-rich Nitride (referredto in the art as a “Yellow Nitride”) and functions as a moistureresistant barrier which inhibits penetration of contaminants such asproton H+ and moisture.

FIG. 4 shows a scanning electron micrograph of an example of thepassivation layer 50′ configuration relative to a contact (C) made ofAluminum.

All three layers 50 a′, 50 b′ and 50 c′ of the stack for the passivationlayer 50′ extend over the exposed upper surface of the premetallizationdielectric layer 32 in areas where the source (S) electrical contact 46and gate (G) electrical contact 48 are not present (see, right side).All three layers 50 a′, 50 b′ and 50 c′ of the stack for the passivationlayer 50′ further extend over sidewalls (S) of the contact C (i.e., onthe side edge surfaces of the lithographically patterned layers 42 and44). The three layers 50 a′, 50 b′ and 50 c′ of the stack for thepassivation layer 50′ further extend over a first surface portion 52 ofthe top surface of the contact C (i.e., on the top surface of thelithographically patterned layer 44). However, only the SiN layer 50 c′extends over a second surface portion 54 of the top surface of thecontact C. The SiN layer 50 c′ (along with flash layer 70, when present)extends on side edge surfaces of the layers 50 a′, 50 b′ at a transitionfrom the first surface portion 52 to the second surface portion 54. Athird surface portion 56 of the top surface of the contact C is notcovered by any of the passivation layer 50′. Additionally, the SiN layer50 c′ extends over sidewalls S1 of the layers 50 a′, 50 b′.

Fabrication of the passivation layer 50′ requires the use of two masksin lithographically patterning the three layers 50 a′, 50 b′ and 50 c′(plus layer 70, if present) of the stack. The steps of the fabricationprocess are shown by FIGS. 5A-5E. In FIG. 5A, the layers 50 a′, 50 b′are deposited over the metal contact C (44). The layers 50 a′ and 50 b′may, for example, be deposited using plasma-enhanced chemical vapordeposition (PECVD). In FIG. 5B, a first mask 60 is formed from adeveloped photoresist. The first mask 60 covers the first surfaceportion 52 of the top surface of the metal contact. An etch is thenperformed to remove portions of the layers 50 a′, 50 b′ which are notcovered by the first mask 60. The first mask 60 is then removed. In FIG.5C, the layer 50 c′ (with interposed Silicon flash layer 70, see FIG. 6,if desired) is conformally deposited to cover the patterned layers 50a′, 50 b′ as well as the second and third surface portions 54 and 56 ofthe top surface of the metal contact. The layer 50 c′ and may, forexample, be deposited using SiH₄-based plasma-enhanced chemical vapordeposition (PECVD). The stoichiometry of the SiN layer 50 c′ may, forexample, comprise Si_(x)N_(y) where the bond ratio x:y, for example,determinable by analysis techniques such as R-ray photoelectronspectroscopy (XPS), Fourier transform infrared spectroscopy (FTIS) orRutherford backscattering (RBS) showing a N/Si ratio that is less thanabout 1.3 (or x:y greater than 3:4) and a refractive index, for examplemeasured by the optical ellipsometry method, that is greater than 2(see, FIG. 7). In FIG. 5D, a second mask 62 is formed from a developedphotoresist. The second mask 62 covers the first and second surfaceportions 52 and 54 of the top surface of the metal contact. An etch isthen performed to remove portions of the layer 50 c′ which is notcovered by the second mask 62 so as to provide a contact opening 64 overthe third surface portion 56 of the top surface of the metal contact.The second mask 62 is then removed. The result is shown in FIG. 5E.

Although FIGS. 3 and 6 show use of the passivation layer 50′ inconnection with a power MOSFET transistor, it will be understood thatthe passivation layer 50′ may be used in connection with the metalcontact/bonding pad of any suitable integrated circuit device. Examplesof such devices include, but are not limited to, a shielded gate trenchpower MOSFET (FIG. 8A) where the passivation is provided at a sourceand/or a gate contact, a trench gate field stop IGBT (FIG. 8B) where thepassivation is provided at an emitter and/or gate contact, asuperjunction MOSFET (FIG. 8C) where the passivation is provided at asource and/or gate contact, and a power diode where the passivation isprovided at an anode and/or cathode contact.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, such illustration and descriptionare considered illustrative or exemplary and not restrictive; theinvention is not limited to the disclosed embodiments. Other variationsto the disclosed embodiments can be understood and effected by thoseskilled in the art in practicing the claimed invention, from a study ofthe drawings, the disclosure, and the appended claims.

What is claimed is:
 1. An integrated circuit device, comprising: a metalcontact having a top surface, the top surface of the metal contactincluding a first surface portion, a second surface portion and a thirdsurface portion; and a passivation layer extending on the first andsecond surface portions of the top surface of the metal contact; whereinthe passivation layer comprises a stack of layers including: atetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS)layer on top of the TEOS layer; and a high-density Silicon-rich Nitridelayer on top of the PTEOS layer; wherein the TEOS and PTEOS layersextend over the first surface portion of the top surface of the metalcontact, but not over the second and third surface portions of the topsurface of the metal contact; and wherein the high-density Silicon-richNitride layer extends over the first and second surface portions of thetop surface of the metal contact, but not over the third surface portionof the top surface of the metal contact.
 2. The integrated circuitdevice of claim 1, wherein the high-density Silicon-rich Nitride layeris in contact with the second surface portion of the top surface of themetal contact.
 3. The integrated circuit device of claim 1, wherein thehigh-density Silicon-rich Nitride layer is in contact with side edgesurfaces of the TEOS and PTEOS layers at a transition from the firstsurface portion to the second surface portion.
 4. The integrated circuitdevice of claim 1, wherein the TEOS layer is in contact with the firstsurface portion of the top surface of the metal contact.
 5. Theintegrated circuit device of claim 1, further comprising a Silicon flashlayer in the stack of layers for the passivation layer, wherein saidSilicon flash layer is positioned between the PTEOS layer and thehigh-density Silicon-rich Nitride layer.
 6. The integrated circuitdevice of claim 5, wherein the Silicon flash layer has a thickness ofless than 100 Å.
 7. The integrated circuit device of claim 5, whereinthe Silicon flash layer is in contact with the second surface portion ofthe top surface of the metal contact.
 8. The integrated circuit deviceof claim 5, wherein the Silicon flash layer is in contact with side edgesurfaces of the TEOS and PTEOS layers at a transition from the firstsurface portion to the second surface portion.
 9. The integrated circuitdevice of claim 5, wherein the high-density Silicon-rich Nitride layeris in contact with the Silicon flash layer.
 10. The integrated circuitdevice of claim 1, wherein the TEOS layer has a thickness in a range ofabout 12,000-16,000 Å.
 11. The integrated circuit device of claim 1,wherein the PTEOS layer has a thickness in a range of about 4,000-6,000Å.
 12. The integrated circuit device of claim 1, wherein thehigh-density Silicon-rich Nitride layer has a thickness in a range ofabout 8,000-12,000 Å.
 13. The integrated circuit device of claim 1,wherein the high-density Silicon-rich Nitride layer has a ratio of N/Sithat is less than about 1.3 and the high-density Silicon-rich Nitridelayer has a refractive index greater than
 2. 14. The integrated circuitdevice of claim 1, wherein a stoichiometry of the high-densitySilicon-rich Nitride layer comprises Si_(x)N_(y) where x:y is greaterthan or equal to 3:4 and the high-density Silicon-rich Nitride layer hasa refractive index greater than
 2. 15. The integrated circuit device ofclaim 1, wherein the metal contact extends over a premetallizationdielectric layer.
 16. The integrated circuit device of claim 12, whereinthe premetallization dielectric layer is formed solely of TEOS.
 17. Theintegrated circuit device of claim 1, wherein the metal contact is agate contact of a discrete transistor.
 18. The integrated circuit deviceof claim 1, wherein the metal contact is a source contact of a discretetransistor.
 19. The integrated circuit device of claim 1, wherein themetal contact includes a sidewall, and wherein the passivation layerfurther extends on the sidewall of the metal contact.
 20. The integratedcircuit device of claim 1, wherein the metal contact is a contact for atransistor source or gate terminal.
 21. The integrated circuit device ofclaim 1, wherein the metal contact is a contact for a transistor emitteror base terminal.
 22. The integrated circuit device of claim 1, whereinthe metal contact is a contact for an anode or cathode terminal of adiode.